Scan architectures are commonly used to test digital circuitry in integrated circuits (IC). Typical scan architectures scan in a test pattern, perform an operation with the test pattern and capture the results, then scan out the results while scanning in the next test pattern in an overlapped fashion. In many low power IC designs, the output buffers are restricted to lower speed operation in order to save power. The total test time is therefore limited by the scan speed determined by the output buffers.
Other features of the present embodiments will be apparent from the accompanying drawings and from the detailed description that follows.